ARM provides developers with intellectual property (IP) solutions in the form of Processors, Physical IP, Systems & platforms, Application - Specific Standard Products (ASSPs), related software and development tools, Multimedia & Graphics solutions - everything you need to create an innovative product design based on industry-standard components that are 'Next Generation' compatible.

With our continued success, we are expanding our operations in Bangalore and are seeking professionals for the various divisions in Bangalore.

Standard Cell - Design & Layout

1. Project Lead / Senior Design Engineers / Design Engineers (Code: SCD)
   • 2-6 years of design experience with deep Submicron technologies. Clear understanding of CMOS Digital Basics with exposure to Circuit Simulation and Optimization is must.
   • Knowledge of scripting in UNIX and Cadence Skill with Standard Cell Design Experience

2. Senior Layout Engineers (Code: SCL)
   • 4+ years in CMOS-related layout design experience with leading CAD tools, design validation including DRC, LVS, ERC, and physical QA.
   • Knowledge of design-for-manufacturability, latch-up, electro-migration, antenna and signal integrity concepts in Physical Design is preferred with familiarity in scripting languages (UNIX, PERL, SKILL)

   Memory - Design & Layout

3. Senior Design Engineers / Design Engineers (Code: MEMD)
   • 2-6 years in CMOS - related SRAM memory design experience
   • Circuit simulation and optimisation, margin analysis, characterization, design validation, including logic simulation and physical verification, layout supervision
   • Familiar with scripting languages (UMIX, shell, PERL, SKILL)
   • Exposure to Hercules and Calibre Verification tools

4. Senior Layout Engineers (Code: MEML)
   • 4+ years of memory compiler layout floor planning, layout analysis (power and critical signals), core cell array development, leaf cell layout
   • Development, full macro layout integration, hierarchical physical verification, layout review and sign-off and layout production level
   • Quality control
   • Exposure to Hercules and Calibre Verification tools

   I/O Design

5. Senior Design Engineer / Design Engineer (Code: IOD)
   • 5+ years of experience design and delivery of I/O cells and AMS blocks. Honds on experience in completing designs for I/O interfaces, like LVDS, PECL, SSTL2, SSTL18, HSTL, high voltage tolerant I/Os, DDR interfaces.
   • Hands on experience in completing designs for AMS blocks, like PLLs, DLLs, DACs.
   • Very good knowledge of layout of the above mentioned I/Os and AMS blocks.
   • Hands on experience in simulation tools like HSPICE and Spectre.
   • Experience in defining and developing infrastructure to deliver above products with high quality and efficiency.
   • High familiarity with Cadence design frame work tools - Composer, Analog Artist, and Virtuoso.

   Software Flows

6. Senior Software Engineers (Code: SF)
   • 5+ years of flow development / design methodology experience, preferably in physical IP development.
   • Ability to analyze existing flows to create high performance standard cell libraries and to architect and implement new improved flows by utilizing internally developed and commercially available EDA tools.
   • Scripting (Shell, Perl, and / or Python) and Flow Automation skills (Makefile, cvs etc.) are a must Extensive experience on EDA tools and flows applicable to standard cell design, characterization, layout creation and verification is needed.
   • Knowledgeable about front-to back-end chip design flows.
   • Web based application development, XML familiarity, Software engineering principles and C++ programming experience desirable.

   DFT Verification

7. Senior Design Engineer / Design Engineer (Code: DFT)
   • 3-5 years RTL verification experience. Experience with BIST / MBIST.
   • Experience in writing, validating and debugging test benches.
   • Experience in developing a test plan.
   • Able to interpret standards and verify conformance.
   • Experience in using Synopsys Design Complier, Prime Time, Verilog simulation, Atrena Spyglass or equivalent tool.
   • Familiarity with Unix scripting and tools.

   CAD Support

8. Senior CAD Support Engineer (Code: CAD)
   • Minimum 3 years experience working with analog EDA tools such as Cadence (Composer, Virtuoso, analog Artist ADE, Spectre, DIVA), Synopsys (HSPICE, Hercules, Star-RCXT) and Mentor Graphics (Calibre).
   • Programming experience using Skill, C, C++, Perl and / or TCL / TK languages.
   • Experience with tool support for mixed-signal IC design.
   • Previous methodology experience with simulation, library development, layout and physical verification.

1. Project Manager (Code: PMPD)
   • 8+ Years experience with proven record of project delivery in an innovative environment
   • Ability to define, plan and execute projects working with engineering teams across international boundaries
   • Excellent communication skills
   • Understanding of silicon, systems and SW design
   • Familiar with design verification methods and tools and/or ASIC implementation and layout and tools
   • Proficient with MS Project or similar EEPM tools

   Processor Implementation

2. Manager / Project Lead / Sr. Design Engineer (Code: PDCI-2)
   • 5-12 year of experience in a processor or ASIC implementation
   • Detailed understanding of synthesis, DFT, LEC, floorplanning, place and route and STA
   • Excellent track record on delivering a number of high profile engineering projects
   • Leadership qualities and good people skills
   • Responsibilities include individual technical contribution, project planning and tracking
   • Maintain high standards of engineering work through technical ability and balanced judgment

3. Design Engineer (Code: PDCI - 1)
   • 1 or more years of experience. Familiarity with design methodologies for the RTL to GDS
   • Detailed knowledge of 90nm and 65nm cell based design flows (using Synopsys / Magma / Cadence)
   • Experience in synthesis, DFT, LEC, floorplanning, place and route and STA
   • Verilog, Tcl / Tk, Perl and CPU architecture knowledge is desirable

   CPU Design Verification

4. Project Lead / Senior DV Engineer (Code: PDCO)
   • 4-8 years of design and/or verification experience in processor or ASIC domain
   • Ability to lead and drive a team of highly skilled engineers
   • Familiar with design verification methodologies and tools
   • VHDL / Verilog, C/C++
   • Assembler programming, Perl / shell scripting
   • Knowledge of Processor architecture and HVLs (Specman-e, Vera) is desirable
   • For the Project Lead role, awareness of project management practices is essential

   Embedded Software Division

5. Senior Design Engineer / Design Engineer (Code: ESD)
   • 1 or more years of experience in embedded software development and optimisation
   • Programming of Mobile or consumer devices
   • Embedded system hardware and software architectures
   • Strong background in one or more of the following:
   • Embedded OS, Device Drivers - Linux, Symbian OS, Windows CE.
   • Multimedia Codecs - MP3 / AAC / MPEG - 4/H.264
   • 3D graphics.
   • Embedded Security.
   • Embedded java Virtual Machine internals.

   Electronics System Level

6. Senior Design Engineers / Engineers (Code: ESL)
   • 1-3 years in experience in C/C++ programming and software development skills in Windows and Unix platforms
   • Working knowledge of scripting tools (Perl, awk, sed, sh) essential
   • Experience with product packaging / release
   • Knowledge of microprocessors (RISC) , SoC designs, knowledge of ARM cores, tools, boards, applications software
   • Systems knowledge of EDA flows for implementation, system and software development
   • Decent understanding of Hardware and SOC concepts
   • Experience in code development on Windows and Unix platforms
   • Familiar with source control systems like CVS or SVN

For positions 1 to 8

For positions A to F

Note: In the email Subject lien indicate the position code, years of relevant experience and current company. Example: Subject SCD, 6 years, Company name

All positions require a minimum BE / B.Tech / M.Tech engineering degree in Electronics, Computer Science Candidates should be self-motivated, quick learners with excellent communication skills,

Freshers: Electronics / Computer Science engineers, please your applications, indicating your branch, aggregate percentage and college name in the subject line of the mail. For more information about ARM please visit our website at www.arm.com