Welcome to Nokia's ASIC Design Centre in Bangalore which is part of our global organization focusing on digital and mixed signal IC development. We deliver verified hardware solutions for all Nokia mobile phone devices, working closely with silicon vendors and system design professionals. Our technology leadership and exceptional motivation helps us meet demanding targets on performance, cost, power consumption, and miniaturization. With the Nokia product offer growing in complexity, cutting edge silicon solutions and high integration ratios are becoming all the more important.

We are looking for ASIC design professionals to work in the areas of system design, high level modeling, front-end specification, power management, VHDL implementation, verification, synthesis, static timing analysis (STA), Design For Test (DFT), floorplan, timing closure, EOA tools support and design database management.

There are opportunities for Design Engineers, Sr. Design Engineers, ASIC Specialists and Team Leaders in our IP development and SoC integration groups.

Module/IP Design (Code: IPDOOI)
Responsible for design and verification of modules/IP blocks for wireless SoC devices.

Skills:

• System design/specification
• Architecture analysis/selection
• SystemC/VHDL/Verilog RTL coding
• Low power design
• Module/IP level verification
• C based HW/SW co-verification
• Synthesis/STA
• Knowledge of UMTS, GPRS, GSM
• Experience in embedded processor.

SoC Front-end Design (code: CHIPD001)
Responsible for front-end design of wireless SoC devices with multiple embedded processors or OSP cores.

Skills:

• SoC architecture and specification
• Low power design and analysis
• VHDL/Verilog RTL coding
• Synthesis and Timing constraints
• RTL and gate level verification
• Embedded processors or DSP.

SoC Verification (Code: COSIM00I)
Responsible for verifying wireless SoC devices with multiple embedded processors or DSP cores.

Skills:

• VHDL/Verilog RTL coding
• Testcase development
• Testbench environment and design
• C based HW/SW co-verification
• RTL and Gate level verification.

SoC Design for Test (Code: DFT001)
Responsible for specifying and executing Design For Test techniques for wireless SoC devices.

Skills:

• Scan, ATPG, JTAG
• Logic BIST, Memory BIST
• Fault simulation
• Knowledge of VLSI test equipment, manufacturing flows. Burn-in and qualification methodologies
• VHDL/Verilog RTL coding.

SoC Back-end Design (Code: DSM001)
Responsible for back-end design of wireless SoC devices.

Skills:

• Synthesis
• Static timing analysis
• Signal integrity and power analysis
• Formal verification
• Timing closure
• Place and Route.

Design Database Management (Code: DDM001)
Responsible for design release and database management.

Skills:

• Synchronicity or ClearCase
• IC design environment setup
• EDA tools setup and support.

At Nokia, the world's largest mobile phone manufacturer and a leading supplier of digital and fixed telecom networks, solutions and products, every challenge is a learning experience. This brings with it growth and opportunities.

To apply, please include the job code in the subject line and send your resume.