Join LSI Logic, Dubai. Work on leading-edge semiconductor technology, and live a cool life.

Call it the best of both worlds, and you're only halfway there. This is your opportunity to work at LSI Logic, Dubai, where you get to be part of a team that will shape great things from the group up.

Started in 1981, LSI Logic Corporation (NYSE: LSI) is a pioneer in System-On-Chip integration. With headquarters in Milpitas, California, LSI Logics Corporation is a leading designer and manufacturer of consumer, communication s and storage semiconductors across the world. Over 4,300 people at about 40 locations worldwide spur out growth by the day. Thanks to them, LSI Logic has been ranked among the top 50 companies worldwide, to be granted patents by the US patent office in 2004.

To move up in life and work, simply choose from the following openings:

Mixed Signal /Analog Design Engineer
Design and development of Analog/MXS cores and products targeted at consumer applications. Opportunity to lead smaller, project focused design teams. Ownership of design, simulation, layout supervision and prototype validation activities. Candidates must demonstrate through understanding of theory and application of Analog/MXS design techniques on deep submicron technologies (90nm, 0.13µm and 0.18µm). Must have experience with commonly used EDA tools for schematic capture, simulation and verification. Prior design and prototype validation experience with Data Converters, PLL's, VCO's, Filters Amplifiers and High Speed Physical Interfaces.

VLSI Design Engineer
Member of design team on next generation, multi-million gate Audio/Video Code SoC's.

Ownership of micro-architectural specification, RTL coding and debug, logic synthesis, analysis and optimization to meet goals for timing, area, power consumption and testability. Participation in silicon debug towards final production release.

Proven ability to code design efficiently in Verilog and proficient in the use of Synopsys logic synthesis tool. Ability work form an abstract specification and complete a design at the 'conceptual' level. Exposure to chip development activities form definition to working silicon. Senior candidates must be able to guide and mentor junior team members.

Physical Design Engineer
As part of the physical design team, candidate will be responsible for all aspects of SoC physical implementation from netlists to GDS, including chip floor plan, power grid design, clock distribution, full chip assembly, P&R, cross talk analysis, RC extraction, EM/IR drop analysis, timing closure, physical verification (DRC/ LVS/ ERC/ Antenna), tapeout and mask review.

Also participate in establishing physical design methodologies and flow automation.

Experience on SoC physical design implementation in 0.13µm, or 0.18µm technology with knowledge of device physics, manufacturing process and DFM. Must be a power user of Synopsys/ Magma P&R tools (Apollo/ Astro/ JupiterXT/ BlastPlan/ BlastFusion). Familiar with hierarchical physical design flow/ methodology-Comfortable in Unix, Perl, Cshell and TCL script writing skills.

CAD Engineer
Modify and maintain Calibre physical verification rule decks form foundries. Able to work with design engineers to resolve physical verification problems and work with process engineers and foundries to resolve rule desk issues and enhancements. Maintaining physical libraries, support circuit simulation issues and physical tapeout of SoC's.

Ability to code Calibre/Hercules DRC, ERC and LVS rule deck base on foundry design rule is a must. Proven experience in circuit simulation, creating extraction deck and setting up Astro/Magma technology files for place and route. Good knowledge in device physics, physical affects in silicon manufacturing is a plus. Experience in Cadence Virtuoso layout tool is a plus. Programming language experiences in either C, PERL or TCL is a must.

Front-End CAD Engineer
Candidate will be part of a dynamic Core Technology front-end team and drive the integration of advanced System-On-Chip (SOC) multimedia designs,

Perform static timing analysis, power optimization, formal verification, placement optimization and signal-integrity timing check. Candidate is also expected to interface with VLSI designers in addressing issues related to front-end tools (synthesis, simulations, static timing, formal verification, RTL and constraints integrity checks) and provide guidance to back-end engineering in completing P&R to meet timing target. Perform evaluation, methodology implementation and productization related to front-end tools. Familiarity with Unix shell level programming in addressing new flow introduction and providing resolutions to users' usage issues.

Qualifications: BSEE/MSEE/PhD from a reputed university with 1 to 5+ years of relevant industry experience. Potential candidates must be strong team players with good and clear communication skills.