Here is an opportunity to work in a full ASIC life cycle, from concept to silicon using Industry-standard EDA tools to provide high quality frontend, backend, analog and mixed-signal design services in domains like Wireless, Telecom and Automotive for global clients.

Tata Eixsi is the Product Design arm of USD 14 billion TATA Group, addressing product design life cycles across various industry verticals, including Automotive, Telecom, Semiconductors, Embedded Systems and Networking.

We offer Product R&D services to customers world-wide, with over a decade's experience in deploying technology for product development. Tata Elxsi is the first company in the world to deploy by SEI CMMI Level 5 assessed custom processes and methodologies exclusively articulated for product design workflow.

We are looking for professionals is the following areas to join our VLSI team:

Logic Design Engineers
Engineers/ Leads with more than 3 years of experience in ASIC/FPGA working in domains like Wireless, Telecom, Automotive and familiar with Processors and BUS interfaces.

Qualification: BE/ ME in ECE/ Micro Electronics.

ASIC DFT Design Engineers/ Lead (Code: LD1)

• Full cycle ASIC experience of at least 2 tape-outs
• Working experience in SCAN insertion, Boundary Scan, BIST, ATPG, Fault grading etc.
• Working knowledge on tools like MBIST, DFT Compiler, Tetramax etc.

Verification Engineers/ Lead (Code: LD2)

• Experience in Conventional Verification using VHDL/ Verilog
• Experience in SystemC
• Experience in Specman Elite/VERA
• Experience in full chip functional verification environment
• Understanding of Processor Architecture is desirable.

Frontend Engineers/ Lead (Code: LD3)

• Experience in RTL coding in Verilog/ VHSL
• Gate level Simulation
• Development of Scripts
• Experience on Synthesis using Design Compiler
• Experience in STA using Primetime
• Experience on Pre-layout Simulation.

Physical Design Engineers

Backend Engineers (Code: PD1)
Qualification: BE/ME in ECE/ Micro Electronics
Experience: 2+ years.

Skill Sets:

• Experience on ASIC Physical design flows.
• Knowledge on DSM Technology
• Proven tool expertise in Floor Planning, Clock Tree Synthesis, SI, Power Routing, Physical Verification & Static Timing sign off.
• Experience in Perl, Tcl.
• Expertise in Magma tools is desirable
• Exposure to synthesis and DFT is desirable.

Analog/ Digital Layout Engineers/ Lead (Code: PD2)
Qualification: Diploma in Electronics or BE/ ME in Electronics.
Experience: 1+ years.

Skill Sets:

• Exposure to Full/ Custom chip layout designs
• Exposure to Layout matching, ESD & Latch up related layout guidelines
• Understanding of deep sub-micron processors
• Understanding layout automation and methodologies Exposure to Cadence tools: Assura, Dracula, Virtuoso
• Knowledge of Physical Design Techniques is desirable.