In the most complex domain of semiconductor solutions we have established global leadership. And we owe our success to our people-fine talents, fiercely focused on defining the future in technologies of tomorrow.

Infineon's Design Automation Technology Group at Bangalore develops leading-edge design flow systems & libraries in latest CMOS technologies like 90nm and 65 nm. In this challenging environment, we offer jobs for technical experts and managers in the following fields.

Analog / Mixed Signal-Technical Expert
Role: Development of methodologies for Full-custom and Mixed Signal Design Automation and Chip/Package Co-Design.

Skills: Analog/Mixed-Signal Simulation •Statistical Analysis/Design for Yield Chip/ Package Co-design •System-In-Package •Package Power Delivery/Signal Integrity •Assembly Rules •RF Design Flows •Automated Custom Physical Design •Skill Programming •Cadence DFII

Layout Verification-Technical Expert & Manager
Role: Integration of EDA tools & Flow Development for Physical Verification in the areas of Layout Verification, Signal Integrity, Parasitic extraction.

Skills: •Layout verification tools (Calibre/ Assura) •Extraction tools (StarRCXT, fire&ice QX, Assura RCX, Calibre XRC) •IR-drop(VoltageStorm) •DSM effects (Crosstalk, IR drop, Antenna) •Astro/ BlastFusion is plus •Cadence DFII •Skill, C++, Tcl.

Physical Implementation-Technical Expert
Role: Integration of EDA tools & development of Place & Route flow including Clock Tree expansion, ECO, etc

Skills: Place & Route (BlastFunsion) •Design Planning •FloorPlanning •Static Timing Analysis • Cross-Talk Analysis • Power Routing • Antenna rules • Tcl

Functional Verification-Technical Expert
Role: Integration of EDA tools (Spyglass), Flow Development for functional verification.

Skills: Logic simulation (ModelSim, CodeCoverage) •E-Language (Specman) •Formal verification (Equivalence/Property checking) •Linting tool (Spyglass)

Formal Verification-Software Engineer
Role: •Design, implementation and testing of GUI or VHDL/ Verilog compliers for equivalence checking, property checking, and intent checking.

Skills: •C++ •GUI (Qt, Tk, Swing) •Knowledge of the application domain: Formal verification, VHDL, Verilog, SystemVerilog, simulation, synthesis

Formal Verification-Application Engineer
Role: •Verification of Customer Design with formal verification tools (intent, property or equivalence checking), training/ expert support for the Asia Pacific region.

Skills: •Formal Verification (assertion, property, equivalence or rule) •Logical/Analytical thinking •Team working and presentation skills

Design System Infrastructure-Software Engineer & Manager
Role: development of Infineon Design System Software infrastructure.

Skills: Knowledge of VLSI/CAD •EDA tool development •OOD (Rational Rose) •Test (Purify/Quality/Purecov, Regression) •C++ (SWIG is a plus) •Web technologies (JavaScript, CGI, HTML, XML) •GUI (Qt, Tk) •Open Access/Milkway is a plus.

Timing SignOff-Technical Expert
Role: Development of Infineon Timing SignOff accuracy tool.

Skills: Knowledge of VLSI/CAD •EDA tool development •OOD (Rational Rose) •Test (Purify / Quantity / Purecov, regression) •C++ •GUI (Qt, Tk) •Static Timing Analysis, Delay calculation, Spice simulation

Front Design Engineer-Test Chip Development
Role: To enable our customers to achieve first-time-right designs by Verification & Characterization of Libraries & New design methodologies on silicon.

Skills: •Logic Design and timing Verification •Test bench and system model development •Production test vector development •Assistance in system debugging and validation •Familiar with EDA tools, including logic simulation, logic synthesis, timing verification, DFT •Experience in RTL coding using VHDL •Good knowledge of digital circuit design and system architecture •Understanding and implementation of test processes and flows •Basic knowledge of standard cells, memory & IO interface Architectures as well as DSM effects, showing up in new technologies

Place & Route Engineer-Cell Libraries
Role: To design leading-edge CMOS standard cell libraries by verifying its usage with P&R tools & flow.

Skills: •Productive generation of views for P&R (e.g. BlastFusion and Apollo/ Astro) of standard cell libraries •Verification of generated views (e.g. all cell P&R, combination of different libraries) •Enable multi VDD and multi Vth P&R concepts-levelshifter; logicswitch (to switch off VDD or VSS of complete blocks); mixing of different Vth Libraries •Support development of libraries with in new process generation e.g. 65 nm •Enable EM verification and yield optimisation within P&R •Enable/ check crosstalk features (analysis/ prevention)

Technical Leader-Memory Compiler Design
Role: To design leading-edge CMOS single and multi-port SRAM & ROM compilers. Duties will include circuit design, SPICE & logic simulation verification, silicon debug, documentation & presentations on various aspects of the design.

Skills: •Minimum 6 years of relevant experience •Memory compilers architecture definition w.r.t. DSM effects •Ultra Low Leakage design •Analog design & mismatch analysis •Timing, Power and Functional Characterisation •GDS and CDL Tiler Programming •Testchip analysis •View modeling for advanced EDA tools •Regression test •Customer Support.

Test Engineer-I/O Libraries
Role: Build-up and maintenance of I/O test lab in Bangalore. Measurements of I/O test chips according of test specification. Design of I/O libraries/ macros.

Skills: •Planning and performance of lab measurements according to test specification •Analysis of test results •Coordination of ESD measurements on library test chips •FE design of I/O libraries •Experience with lab measurements/ electrical measurements •Experience in analog circuit design and in HF measurements is a plus.

Find our more about the above positions at: www.infineon-jobs.com/jobs/ Click on the "Bangalore" link.

All the positions,

• Are based at Bangalore, just 4 hours time difference from our headquarters in Europe.
• Require: •B.E/B. Tech/ME/M. Tech/Ph.D •Skills in Unix, Clearcase and Perl •Good communication skills (fluency in English) •4+ years of experience

Please send your resume, to the respective e-mail Ids. Mention contact number, skill set & domain expertise, years of experience.

Confidential interviews can be arranged on request for Section Managers & Technical Leaders (6+ years experience). Mention 'Confidential' in the subject line.

Candidates with less than 1 year of experience are requested to send their resume.

Fact File
Fastest growing among the world's top 10 semiconductor companies
1800 products across 135 countries
30,000+ employees worldwide
Over 34,000 patents
Turnover of 6.15 Euro billion in 2003.