We build the foundation for future smiconductor Solutions
Fact File
Fastest growing among the world's top 10 semiconductor companies
1800 products across 135 countries
30,000+ employees worldwide
Over 34,000 patents
Turnover of 6.15 Euro billion in 2003.
In the most complex domain of semiconductor solutions we have established global leadership. And we owe our success to our people-fine talents, fiercely focused on defining the future in technologies of tomorrow.
Infineon's Design Automation Technology Group at Bangalore develops leading-edge design flow systems & libraries in latest CMOS technologies like 90nm and 65 nm. In this challenging environment, we offer jobs for technical experts and managers in the following fields.
IC Design Flow & Methodology
Analog / Mixed Signal
Role: Development/ Evaluation of methodologies/flows for Analog and Custom Design as well as for Chip/Package Co-Design.
Skills: Simulation/Device Modeling Statistical Analysis/Design for Yield Substrate Noise System-In-Package System Interconnect Modelling Custom Digital STA Layout Capture/ Custom Design Environments Cadence DFII environment (Skill) Cadence APD Spice VHDL-AMS, Verilog-A Assura, Calibre DesignSync is a plus.
Layout Verification
Role: Integration of EDA tools & Flow Development for Physical Verification in the areas of Layout Verification, Signal Integrity, Parasitic extraction.
Skills: Layout verification tools (Calibre/ Assura) Extraction tools (StarRCXT, fire&ice QX, Assura RCX, Calibre XRC) IR-drop(VoltageStorm) DSM effects (Crosstalk, IR drop, Antenna) Astro/ BlastFusion is plus Cadence DFII Skill, C++, Tcl.
Timing SignOff
Role: Development of Infineon Timing SignOff accuracy tool.
Skills: Knowledge of VLSI/CAD EDA tool development OOD (Rational Rose) Test (Purify / Quantity / Purecov, regression) C++ GUI (Qt, Tk) Static Timing Analysis, Delay calculation, Spice simulation
Functional Verification
Role: Integration of EDA tools, Flow Development for functional verification, Software development of formal verification tools and application support.
Skills: Logic simulation (ModelSim, CodeCoverage) E-Language (Specman) Formal verification Equivalence/Property checking) Linting tool System Verilog Tcl C++ GUIs with Qt, Gtk, Swing Compiler construction Agile development.
Design System Infrastructure
Role: development of Infineon design System Software infrastructure.
Skills: Knowledge of VLSI/CAD EDA tool development OOD (Rational Rose) Test (Purify/Quality/Purecov, Regression) C++ (SWIG is a plus) Web technologies (JavaScript, CGI, HTML, XML) GUI (Qt, Tk) Open Access/Milkway is a plus.
Physical Implementation
Role: Integration of EDA tools & development of Place & Route flow including Clock Tree expansion, ECO, etc
Skills: Place & Route (BlastFunsion) Design Planning FloorPlanning Static Timing Analysis Cross-Talk Analysis Power Routing Antenna rules Tcl
Expert Support / Application Engineer
Role: support for IC design flow/EDA tool of Infineon hardware design projects, IC design flow infrastructure, setup and administration of IC project design environment. Your customers will be infineon IC development experts all over the world
Skills: In-depth methodical knowledge of IC development and hands-on experience in at least one of the areas of system verification, design implementation or layout verification Hands-on experience with EDA tools from Synopsys, Cadence, Magma or Mentor expertise is Clearcase, LSF, Unix, Perl & EDA license management is a plus Very good communication and customer orientation skills.
Library Design
Library Test Chip Design
Role: To enable our customers to achieve first-time-right designs by Verification & Characterization of Libraries & New design methodologies on silicon.
Skills: Successful candidate will have strong skills in chip physical design methodology, flows and tools such as LVS/DRC, Place & Route, Extraction, Timing closure, Synthesis, DFT; must be experienced in corking with backend IP: gds, netlist, lef, def, lib views of standard and custom cells; and have, SRAMs & IO interface Architectures as well as DSM effects, showing up in new technologies Ability to develop new circuits. Knowledge of manufacturing processes and experience of going through actual tape-outs of chips will be plus. Provide technical leadership and project management of the team.
Cell Library
Role: To design leading-edge CMOS standard cell libraries.
Skills: Standard Cell Library architecture, design, layout, test chip, characterization, design kit generation and distribution Design optimization and electrical characterization Place & Route View modeling for advanced EDA tools Automation of library generation Layout extraction and versification tolls Experience with industry standard tools from Cadence/Synopsys/Mentor/Magma
Memory Compilers
Role: To design leading-edge CMOS single and multi-port SRAM, ROM & Flash compilers. Duties will include circuit design, SPICE & logic simulation verification, silicon debug, documentation & presentations on various aspects of the design.
Skills: A thorough understanding of different memory architectures, behavioral modeling, logic/circuit design and simulation, power characterization, memory compiler code development, UNIX and/or CAD methodologies Be familiar in the use of redundancy and BIST Low Power & Low Leakage design w.r.t DSM effects Timing & Power characterization Design for Manufacturability Functional & silicon verification Must have debug skills & knowledge of simulators, custom IC layouts, and basic CMOS IC processing.
All the positions are based at Bangalore, just 4 hours time difference from our headquarters in Europe.
For all positions, you should have:
Please send your resume, to the respective e-mail Ids. Mention contact number, years of experience, skill set and domain expertise, in the subject line.
Human Resources Department,
Infineon Technologies India Pvt. Ltd.,
13th Floor, Discoverer Building,
International Tech Park,
Whitefield Road, Bangalore-560 066. India.
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