In the most complex domain of semiconductor solutions - we have established global leadership. And we owe our success to our people - fine talents, fiercely focused on defining the future in technologies of tomorrow. If you are one of those rare professionals, who has the courage and passion to build invaluable experience in design automation/library development, you can translate your expertise into global competence and unbridled growth.

Infineon Technolgies AG, Munich, Germany-one of the top ten semiconductor companies in the world-offers semiconductor companies in the world-offers semiconductor and systems solutions for applications in the wired and wireless communications markets; security systems and smart cards; automotive and industrial sectors; as well as memory products. With a strong global presence-operating from San Jose (CA) in US, Singapore in Asia Pacific, and Tokyo in Japan Infineon reaches out to 135 countries with 1800 products, relying on the stregth of 30000+ professionals worldwide. In the fiscal year ending September 2003, the company achieved sales of Eruo 6.15 billion. Infineon is listed on the DAX index of the Frankfurt Stock Exchange and the New York Stock Exhange (Ticker Symbol: IFX).

For our Design Automation Technology Group at India Development Centre, Bangalore, where we develop world-class, leading-edge Design Flow Systems & Libraries for the latest CMOS Technologies - with a focus on 90 nm and pre-development for 65 nm, we need highly-motivated engineering professionals in the areas of IC Design Flow and Library Design, to join us as:

Section Managers:
Lead, Motivate & give technical guidance to groups of 10+ people; are responsible for customer contacts, recruiting & productivity. 8+ years of relevant experience.

Technical Leaders:
Experts in one of the described fields; supervise team members participate in technical reviews; give imputs to improve products. 5+ years of relevant experience.

IC Design Flow & Methodology

Analog/Mixed Signal - Section Manager & Technical Leaders

Role: Integration of EDA tools, development of Analog/Mixed- Singal design methodology for future DSM technologies and expert application support.

Skills:

• Cadence DFII environment
• Layout Generators
• Circuit Simulators (Spice, Statistical circuit analysis, VHDL-AMS, Verilog - A) Timing Characterisation (STA, Assura, Calibre)
• Chip/Package Co-design
• Design for Manufacturability
• Skill
• DesignSync is a plus.

To Apply, Click here!

Physical Implementation - Technical Leaders

Role: Integration of EDA tools & Physical Flow Development-Synthesis, Place & Route, Clock Tree Expansion, ECO, etc.

Skills:

• Power Analysis (Power/Theatre)
• Logical/Physical synthesis (Design/Physical Compiler)
• Place & Route (Blast Fusion)
• Design Planning (First Encounter)
• Tcl.

To Apply, Click here!

Layout Vertification - Section Manager & Technical Leaders

Role: Integration of EDA tools & Flow Development for physical layout vertification in the areas of signal integrity, DRC, LVS.

Skills:

• Layout vertification tools (Calibre/Assura)
• Extraction tools (StarRCXT or fire&ice QX)
• DSM effects (Crosstalk, IR drop, Antenna)
• Physical Compiler/BlastFusion/FirstEnvounter is a Plus
• VoltageStorm
• Codence DFII
• C++, Tcl, Skill.

To Apply, Click here!

Functional Vertification - Technical Leaders

Role: Integration of EDA tools, Flow Development for functional vertification and application support.

Skills:

• Logic simulation (ModelSim, CodeCoverage)
• E-Language (Specman)
• Formalvertification (Equivalence/Property checking)
• Linting tools
• Tcl
• System Verilog.

To Apply, Click here!

Design System Infrastruture - Section Manager & Technical Leaders

Role: Development of Infineon Design System Software infrastructure.

Skills:

• OOD (Rational Rose)
• EDA tool development
• Basics of VLSI
• Test (Purify/Quantify/Purecov, regression)
• C++ (SWIG is aplus)
• Web technogies (JavaScript, CGI, HTML, XML)
• GUI (Qt, TK)
• Open Access/Milkyway is a plus.

To Apply, Click here!

Expert Support/Application Engineer

Role: Support for IC Design Teams on design flow and EDA tool related topics.

Skills: In-depth methodical knowledge and hands-on experience in at least one of the areas of: System verification, Design implementation and Layout vertification-
Very good communication and customer orientation skills.

To Apply, Click here!

Library Design

Library Test Chip Design - Section Manager & Technical Leaders

Role: To enable our customers to achieve first-time-right design by Verification & Characterisation of Libraries & New Design methodologies on silicon.

Skills:

• Experience on design, Layout & vertification of complex Ics using modern EDA tools
• Basic knowledge of standard cells, SRAMs & IO interface Architectures as well as DSM effects, showing up in new technogies
• Ability to develop new circuits.

To Apply, Click here!

Cell Library - Technical Leaders

Role: To design leading -edge CMOS standard libraries.

Skills:

• Design, Optimisation and electrical characterization
• Place & Route
• View modeling for advanced EDA tools
• Automation of library generation
• Experience with industry standard tools from Cadence/ Synopsys/ Mentor/ Magma

To Apply, Click here!

Memory Compilers - Technical leders

Role: To design leading - edge CMOS SRAM & ROM compliers.

Skills:

• Low Power & Low Leakage Design w.r.t DSM effects
• Timing & Power characterization
• Design for Manufacturability
• Functional & Silicon vertification.

To Apply, Click here!

For all the above positions you should also have skills in Unix, Clearcase, and Perl with good communication.

If the prospect of a challenging career with a global major excites you, please send your resume, to the respective e-mail Ids.

Please mention contact number, years of experience, skill set and domain expertise, in the subject line. For all the positions, applicants would be BE/ B.Tech/ ME/ M.Tech/ Ph.D with relevant experience.