Infineon Technologies AG, Munich, Germany - one of the top six Semiconductor companies in the world-offers semiconductor and systems solutions for applications in the wired & wireless communications markets; security systems and smart cards; automotive and industrial sectors; and memory products. With a strong global presence - operating from San Jose (CA) in US, Singapore in Asia Pacific, and Tokyo in Japan - Infineon reaches out to 135 countries with 1800 products, relying on the strength of 30000+ professionals worldwide. In the fiscal year ending September 2003, the company achieved sales of Euro 6.15 billion. Infineon is listed on the DAX index of the Frankfurt Stock Exchange and the New York Stock Exchange (Ticker symbol: IFX)

We've streamlined our wireline communication portfolio to address the fast growing internet infrastructure marketplace. The Optical Networking Group in Infineon develops cutting-edge multi-million gate designs. These are 10M+ gates in 0.14( technology with 1000+ pin Flip Chip Packages with integrated multiple 3/125 Gbps serdes links and various communication protocol processors. The optical Networking Group has a track record of creating first time working silicon, which are designed into tier-1 Networking customers. These complex developments have been pushing the EDA developments, design methodology and technology to its edge. Join this team at Bangalore to accelerate your career with world-class silicon solutions.

Staff Engineers (8+ experience)
Sr. Engineers (4+ experience)
Engineers (3+ experience)

ASIC Design and Verification

• Minimum 3 years experience in concept and micro-architecture specification through design tapeout of a multi-million SOC for Networking/Telecom domain
• Knowledge of Networking standards and concepts-SONET/SDH, EOS, VCAT/LCAS, RPR etc.
• Experience in using simulation, synthesis, linting, code coverage, PERL, C/C++
• Experience in chip level RTL integration desirable.

ASIC Layout and Implementation

• Minimum 4 years experience in layout, timing closure and DFT of a multi-million SOC
• Hands-on experience with full chip floorplanning, P&R, timing closure, signal integrity, DFT tools, formal verification, parasitic extraction, physical verification, voltage drop and electro-migration.
• Understanding of mixed-signal IP integration, high speed multiple clock domains and power grid design.

Software Engineers

• Experience in developing embedded and systems software
• Strong in C/C++, UNIX, and preferably VxWorks and/or pSOS
• Experience with HW/SW interface and HW bring up issues
• Knowledge of SONET/SDH, Ethernet, L2/L3 protocols (MPLS, VPN), SNMP, CMIP & TL1.

Walk in interview for candidates with 3-6 years experience on 17th April 2004 at:

Those unable to walk in, may mail their resumes. (Mentioning contact number, years of relevant experience and domain expertise in the subject).

We are currently not looking for freshers & MCAs.